Semiconductor package and method for making the same

ABSTRACT

The present invention relates to a semiconductor package and a method for making the same. The method includes the steps of: (a) providing a base material; (b) forming a first metal layer on the base material, wherein the first metal layer comprises a first inductor and a first lower electrode; (c) forming a first dielectric layer and a first upper electrode on the first lower electrode, wherein the first dielectric layer is disposed between the first upper electrode and the first lower electrode, and the first upper electrode, the first dielectric layer and the first lower electrode form a first capacitor; and (d) forming a first protective layer, so as to encapsulate the first inductor and the first capacitor.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a divisional application of U.S. patentapplication Ser. No. 12/795,357 filed on Jun. 7, 2010, and is herebyincorporated by reference herein in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor package and a methodfor making the same, and more particularly, to a semiconductor packagewith passive devices integrated therein and a method for making thesame.

2. Description of the Related Art

FIG. 1 shows a cross-sectional view of a conventional semiconductorpackage. As shown in FIG. 1, the conventional semiconductor package 1comprises a substrate 11, a packaged unit 12 and a molding compound 13.The packaged unit 12 comprises a plurality of passive devices (notshown). The packaged unit 12 is disposed on and is electricallyconnected to the substrate 11. The molding compound 13 encapsulates thepackaged unit 12.

The conventional semiconductor package I has following defects. Sincethe passive devices are first integrated in the packaged unit 12 byusing a semiconductor process and the packaged unit 12 is thenelectrically connected to the substrate 11 by wire bonding or flip-chipbonding (not shown), thus causing a complicated process of integratingthe passive devices in the packaged unit 12 and a high production cost.

Consequently, there is an existing need for a semiconductor package anda method for making the same that solves the above-mentioned problems.

SUMMARY OF THE INVENTION

The present invention provides a method for making a semiconductorpackage. The method comprises the steps of: (a) providing a basematerial; (b) forming a first metal layer on the base material, whereinthe first metal layer comprises a first inductor and a first lowerelectrode; (c) forming a first dielectric layer and a first upperelectrode on the first lower electrode, wherein the first dielectriclayer is disposed between the first upper electrode and the first lowerelectrode, and the first upper electrode, the first dielectric layer andthe first lower electrode form a first capacitor; and (d) forming afirst protective layer, so as to encapsulate the first inductor and thefirst capacitor.

Whereby, the first inductor and the first lower electrode of the firstcapacitor are formed simultaneously on the same layer, so as to achievethe effect of integrating plural passive devices and improve theproduction efficiency.

The present invention further provides a semiconductor package. Thesemiconductor package includes a base material, a first metal layer, afirst dielectric layer, a first upper electrode and a first protectivelayer. The base material has a first surface and a second surface. Thefirst metal layer is disposed on the first surface of the base materialand includes a first inductor and a first lower electrode. The firstdielectric layer is disposed on the first lower electrode. The firstupper electrode is disposed on the first dielectric layer, and the firstupper electrode, the first dielectric layer and the first lowerelectrode form a first capacitor. The first protective layerencapsulates the first inductor and the first capacitor.

The present invention further provides a semiconductor package. Thesemiconductor package includes a base material, a first dielectriclayer, a first upper electrode and a first protective layer. The basematerial has a first surface, a second surface, at least one groove andat least one through via structure. The groove penetrates the firstsurface and the second surface. The through via structure is disposed inthe groove and exposed on the first surface and the second surface. Thefirst metal layer is disposed on the first surface of the base materialand includes a first inductor and a first lower electrode. The firstmetal layer directly contacts the through via structure. The firstdielectric layer is disposed on the first lower electrode, and the firstupper electrode is disposed on the first dielectric layer. The firstupper electrode, the first dielectric layer and the first lowerelectrode form a first lay capacitor. The first protective layerencapsulates the first inductor and the first capacitor.

Whereby, the first inductor and the first lower electrode of the firstcapacitor are disposed on the same layer, so that the thickness of theproduct is reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a conventional semiconductorpackage;

FIGS. 2-18 are schematic views of a method for making a semiconductorpackage according to a first embodiment of the present invention;

FIG. 19 is a cross-sectional view of a semiconductor package accordingto a second embodiment of the present invention;

FIGS. 20-26 are schematic views of a method for making a semiconductorpackage according to the second embodiment of the present invention; and

FIGS. 27-29 are schematic views of a method for making a semiconductorpackage according to a third embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 2-19 are schematic views of a method for making a semiconductorpackage according to a first embodiment of the present invention. Asshown in FIG. 2, a base material 21 is provided. In this embodiment, thebase material 21 comprises a first surface 211, a bottom surface 212, atleast one outer groove 213 and at least one conductive via structure217. The outer groove 213 opens at the first surface 211 of the basematerial 21. The conductive via structure 217 is disposed in the outergroove 213 and exposed on the first surface 211 of the base material 21.

In this embodiment, the base material 21 is made of non-insulationmaterial such as silicon or germanium. The conductive via structure 217comprises an outer insulation layer 2141, a conductor 2142 and an innerinsulation layer 2143. The outer insulation layer 2141 is disposed onthe side wall of the outer groove 213 to define a first central groove2144, the conductor 2142 is disposed on the side wall of the firstcentral groove 2144 so as to define a second central groove 2145, andthe second central groove 2145 is filled with the inner insulation layer2143. In other embodiments, the outer insulation layer 2141 can also bedisposed on the bottom wall of the outer groove 213 (not shown). Sincethe base material 21 is made of non-insulation material, the outerinsulation layer 2141 is used to insulate the base material 21 and theconductor 2142 to avoid the current which passes through the conductivevia structure 217 being conducted to the base material 21 and reducingthe electrical effects of the conductive via structure 217.

However, in other embodiments, as shown in FIG. 3, the conductive viastructure 217 can only comprise an outer insulation layer 2141 and aconductor 2142 but does not comprise the inner insulation layer 2143(FIG. 2). The outer insulation layer 2141 is disposed on the side wallof the outer groove 213 to define a first central groove 2144, and thefirst central groove 2144 is filled with the conductor 2142. Inaddition, the base material 21 can be made of insulation material suchas glass or silica, and the conductive via structure 217 may notcomprise the outer insulation layer 2141 (FIG, 2). Therefore, as shownin FIG. 4, the conductive via structure 217 can only comprise aconductor 2142 and an inner insulation layer 2143, wherein the conductor2142 is disposed on the side wall and the bottom portion of the outergroove 213 to define a second central groove 2145, and the secondcentral groove 2145 is filled with the inner insulation layer 2143.Alternatively, as shown in FIG. 5, the conductive via structure 217 canonly comprise a conductor 2142, wherein the outer groove 213 is filledwith the conductor 2142. As shown in FIG. 6, a first passivation layer22 is formed on the base material 21. In this embodiment, the firstpassivation layer 22 is formed on the first surface 211 of the basematerial 21 and has a first through hole 221, and the first through hole221 exposes the conductive via structure 217.

Then, a first metal layer 23 (FIG. 9) is formed on the base material 21.The first metal layer 23 includes a first inductor 231 and a first lowerelectrode 232. In this embodiment, the first metal layer 23 is formed onthe first passivation layer 22 and directly contacts the conductive viastructure 217. In this embodiment, the steps of forming the first metallayer 23 are described as follows. As shown in FIG. 7, a first seedlayer 233 is formed on the base material 21. As shown in FIG. 8, a firstphotoresist 234 is formed on the first seed layer 233 so as to coverpart of the first seed layer 233 and expose part of the first seed layer233, and a first plated layer 235 is formed on the exposed part of thefirst seed layer 233. As shown in FIG. 9, the first photoresist 234(FIG. 8) and the covered part of the first seed layer 233 are removed,wherein the first plated layer 235 and part of the first seed layer 233form the first metal layer 23.

Then, a first dielectric layer 24 (FIG, 11) and a first upper electrode25 (FIG. 11) are formed on the first lower electrode 232. The firstdielectric layer 24 is disposed between the first upper electrode 25 andthe first lower electrode 232, and the first upper electrode 25, thefirst dielectric layer 24 and the first lower electrode 232 form a firstcapacitor 26 (FIG. 11). In this embodiment, the steps of forming thefirst dielectric layer 24 are described as follows. As shown in FIG. 10,firstly, a second metal layer is formed (for example, by sputtering) onthe first lower electrode 232, and the second metal layer is anodized,so as to form a first oxidation layer 241. The second metal layer ismade of tantalum (Ta), and the first oxidation layer 241 is made oftantalum pentoxide (Ta₂O₅). Then, a third metal layer 251 is formed (forexample, by sputtering) on the first oxidation layer 241, wherein thethird metal layer 251 is made of AlCu. Finally, a second photoresist 261is formed on the third metal layer 251. As shown in FIG. 11, part of thefirst oxidation layer 241 (FIG, 10) and part of the third metal layer251 (FIG. 10) are removed, so as to form the first dielectric layer 24and the first upper electrode 25, respectively. Meanwhile, the firstcapacitor 26 is formed, and the second photoresist 261 (FIG. 10) isremoved. As shown in FIG. 12, a first protective layer 27 is formed, soas to encapsulate the first inductor 231 and the first capacitor 26. Thefirst protective layer 27 comprises at least one first opening 271, andthe first opening 271 exposes part of the first metal layer 23 or partof the first upper electrode 25.

Then, at least one first bump 28 (FIG. 15) is formed in the firstopening 271 of the first protective layer 27. In this embodiment, thesteps of forming the first bump 28 are described as follows. As shown inFIG. 13, a second seed layer 281 is formed on the first protective layer27. As shown in FIG. 14, a third photoresist 282 is first formed on thesecond seed layer 281, so as to cover part of the second seed layer 281and expose part of the second seed layer 281. Then, a second platedlayer 283 is formed on the exposed part of the second seed layer 281. Asshown in FIG. 15, the third photoresist 282 and the covered part of thesecond seed layer 281 are removed, so as to form the first bump 28.

As shown in FIG. 16, the base material 21 is disposed on a carrier 29,wherein the first surface 211 of the base material 21 faces the carrier29. Part of the base material 21 is removed from the bottom surface 212(FIG. 15), to form a second surface 215 and to expose the conductor 2142of the conductive via structure 217 (FIG. 15) on the second surface 215,so as to form a through via structure 214. However, in otherembodiments, more part of the base material 21 can be further removed,so that the inner insulation layer 2143 of the conductive via structure217 (FIG. 15) is also exposed on the second surface 215, which canensure that the conductor 2142 is exposed on the second surface 215.

As shown in FIG. 17, at least one electrical device is formed on thesecond surface 215 of the base material 21. In this embodiment, theelectrical device is a second bump 31, and the method for making thesecond bump 31 is the same as that for making the first bump 28 andtherefore not described in detail. As shown in FIG. 18, the carrier 29is removed, and a semiconductor package 2 according to a firstembodiment of the present invention is made. However, the electricaldevice can be a second inductor 32 and a second capacitor 33, as shownin FIG. 19. The method for making the second inductor 32 and the secondcapacitor 33 is the same as that for making the first inductor 231 andthe first capacitor 26. That is, the manufacturing process applied tothe second surface 215 of the base material 21 is the same as thatapplied to the first surface 211 of the base material 21 and thereforenot described in detail.

As a result, the first inductor 231 and the first lower electrode 232 ofthe first capacitor 26 are formed simultaneously on the same layer, sothe effect of integrating plural passive devices can be achieved and theproduction efficiency can be improved.

FIG. 18 shows a cross-sectional view of the semiconductor packageaccording to the first embodiment of the present invention. As shown inFIG. 18, the semiconductor package 2 includes a base material 21, afirst passivation layer 22, a second passivation layer 34, a first metallayer 23, a first dielectric layer 24, a first upper electrode 25, afirst protective layer 27, at least one first bump 28 and at least oneelectrical device. The base material 21 has a first surface 211, asecond surface 215, at least one outer groove 213 and at least onethrough via structure 214. The outer groove 213 penetrates the firstsurface 211 and the second surface 215. The through via structure 214 isdisposed in the outer groove 213 and exposed on the first surface 211and the second surface 215. However, in other embodiments, the basematerial 21 may not comprise the outer groove 213 and the through viastructure 214.

In this embodiment, the base material 21 is made of non-insulationmaterial such as silicon or germanium. The through via structure 214comprises an outer insulation layer 2141, a conductor 2142 and an innerinsulation layer 2143. The outer insulation layer 2141 is disposed onthe side wall of the outer groove 213 to define a first central groove2144, the conductor 2142 is disposed on the side wall of the firstcentral groove 2144 so as to define a second central groove 2145, andthe second central groove 2145 is filled with the inner insulation layer2143. Since the base material 21 is made of non-insulation material, theouter insulation layer 2141 is used to insulate the base material 21 andthe conductor 2142 to avoid the current which passes through the throughvia structure 214 being conducted to the base material 21 to reduce theelectrical effects of the through via structure 214.

However, in other embodiments, the through via structure 214 can onlycomprise an outer insulation layer 2141 and a conductor 2142 but doesnot comprise the inner insulation layer 2143. The outer insulation layer2141 is disposed on the side wall of the outer groove 213 to define afirst central groove 2144, and the first central groove 2144 is filledwith the conductor 2142. In addition, the base material 21 can be madeof insulation material such as glass or silica, and the through viastructure 214 may not comprise the outer insulation layer 2141.Therefore, the through via structure 214 can only comprise a conductor2142 and an inner insulation layer 2143, wherein the conductor 2142 isdisposed on the side wall of the outer groove 213 to define a secondcentral groove 2145, and the second central groove 2145 is filled withthe inner insulation layer 2143. Alternatively, the through viastructure 214 can only comprise a conductor 2142, and the outer groove213 is tilled with the conductor 2142.

The first passivation layer 22 is formed on the first surface 211 of thebase material 21 and has a first through hole 221, and the first throughhole 221 exposes the through via structure 214. The second passivationlayer 34 is disposed on the second surface 215 of the base material 21and has a second through hole 341, and the second through hole 341exposes the through via structure 214. The first metal layer 23 isformed on the first surface 211 of the base material 21. Preferably, thefirst metal layer 23 is formed on the first passivation layer 22,includes a first inductor 231 and a first lower electrode 232, anddirectly contacts the through via structure 214. The first dielectriclayer 24 is disposed on the first lower electrode 232. In thisembodiment, the first dielectric layer 24 is made of tantalum pentoxide(Ta₂O₅). The first upper electrode 25 is disposed on the firstdielectric layer 24, and the first upper electrode 25, the firstdielectric layer 24 and the first lower electrode 232 form a firstcapacitor 26. In this embodiment, the first upper electrode 25 is madeof AlCu.

The first protective layer 27 encapsulates the first inductor 231 andthe first capacitor 26. In this embodiment, the first protective layer27 comprises at least one first opening 271, and the first opening 271exposes part of the first metal layer 23 or part of the first upperelectrode 25. The first bump 28 is disposed in the first opening 271 ofthe first protective layer 27. The electrical device is disposed on thesecond surface 215 of the base material 21. The electrical device is asecond bump 31.

As a result, the first inductor 231 and the first lower electrode 232 ofthe first capacitor 26 are disposed on the same layer, so that thethickness of the product is reduced.

FIG. 19 shows a cross-sectional view of the semiconductor packageaccording to a second embodiment of the present invention. As shown inFIG. 19, the semiconductor package 3 of the second embodiment and thesemiconductor package 2 (FIG. 18) of the first embodiment aresubstantially the same, and the same elements are designated with thesame numerals. The difference between the second embodiment and thefirst embodiment is that the second surface 215 of the semiconductorpackage 3 further comprises a plurality of electrical devices such as asecond inductor 32, a second capacitor 33 and a second bump 31.

FIGS, 20-26 are schematic views of a method for making a semiconductorpackage according to the second embodiment of the present invention. Asshown in FIG. 20, a base material 21 is provided. In this embodiment,the base material 21 comprises a top surface 216 and a second surface215. The outer groove 213 opens at the second surface 215 of the basematerial 21, and the conductive via structure 217 is exposed on thesecond surface 215 of the base material 21. As shown in FIG. 21, asecond passivation layer 34 is formed on the base material 21. In thisembodiment, the second passivation layer 34 is disposed on the secondsurface 215 of the base material 21 and has a second through hole 341,and the second through hole 341 exposes the conductive via structure217. Then, at least one electrical device is formed on the secondsurface 215 of the base material 21, preferably on the secondpassivation layer 34. In this embodiment, the electrical device is asecond bump 31. As shown in FIG. 22, the base material 21 is disposed ona carrier 29, wherein the second surface 215 of the base material 21faces the carrier 29. Part of the base material 21 is removed from thetop surface 216 (FIG. 21), to form a first surface 211 and to expose theconductive via structure 217 (FIG. 21) on the first surface 211, so asto form a through via structure 214.

As shown in FIG. 23, a first metal layer 23 is formed on the basematerial 21, preferably on the first surface 211 of the base material21. A first plated layer 235 and a first seed layer 233 form the firstmetal layer 23. The first metal layer 23 includes a first inductor 231and a first lower electrode 232. As shown in FIG. 24, a first dielectriclayer 24 and a first upper electrode 25 are formed on the first lowerelectrode 232. The first dielectric layer 24 is disposed between thefirst upper electrode 25 and the first lower electrode 232, and thefirst upper electrode 25, the first dielectric layer 24 and the firstlower electrode 232 form a first capacitor 26. As shown in FIG. 25, afirst protective layer 27 is formed, so as to encapsulate the firstinductor 231 and the first capacitor 26. The first protective layer 27comprises at least one first opening 271, and the first opening 271exposes part of the first metal layer 23 or part of the first upperelectrode 25. As shown in FIG. 26, at least one first bump 28 isthrilled in the first opening 271 of the first protective layer 27 andthe carrier 29 is removed, and the semiconductor package 2 is made.

FIGS. 27-29 are schematic views of a method for making a semiconductorpackage according to a third embodiment of the present invention. Themethod for making a semiconductor package of the third embodiment issubstantially the same as that (FIGS. 2-19) of the first embodiment ofthe present invention, and the same elements are designated with thesame numerals. The difference between the third embodiment and the firstembodiment, as shown in FIG. 27, is that the base material 21 having afirst surface 211, a second surface 215, at least one outer groove 213and at least one conductive via structure is provided. The outer groove213 penetrates the first surface 211 and the second surface 215. Theconductive via structure is disposed in the outer groove 213 and exposedon the first surface 211 and the second surface 215, so as to form athrough via structure 214. Then, as shown in FIG. 28, firstly, a firstinductor 231 and a first capacitor 26 are formed on the first surface211 of the base material 21. As shown in FIG. 29, secondly, at least oneelectrical device is formed on the second surface 215 of the basematerial 21, and the semiconductor package 2 is made. However, in otherembodiments, the base material 21 can only comprise a first surface 211and a second surface 215 but does not comprise the outer groove 213(FIG. 27) and the through via structure 214 (FIG. 27). Besides, theelectrical device can first be formed on the second surface 215 of thebase material 21, and then the first inductor 231 and the firstcapacitor 26 are formed on the first surface 211 of the base material21.

While embodiments of the present invention have been illustrated anddescribed, various modifications and improvements can be made by thoseskilled in the art. The embodiments of the present invention aretherefore described in an illustrative but not restrictive sense. It isintended that the present invention is not limited to the particularforms illustrated, and that all modifications that maintain the spiritand scope of the present invention are within the scope defined in theappended claims.

What is claimed is:
 1. A method for making a semiconductor package,comprising the steps of (a) providing a base material, wherein the basematerial comprises at least one groove, at least one conductive viastructure, a first surface and a second surface, the groove penetratesthe first surface and the second surface of the base material, and theconductive via structure is disposed in the groove and exposed on thefirst surface and the second surface so as to form a through viastructure; (b) forming a first metal layer on the first surface of thebase material, wherein the first metal layer comprises a first inductorand a first lower electrode, and directly contacts the through viastructure; (c) forming a first dielectric layer and a first upperelectrode on the first lower electrode, wherein the first dielectriclayer is disposed between the first upper electrode and the first lowerelectrode, and the first upper electrode, the first dielectric layer andthe first lower electrode form a first capacitor; and (d) forming afirst protective layer, so as to encapsulate the first inductor and thefirst capacitor.
 2. The method according to claim 1, further comprisinga step of forming a first insulation layer on the first surface of thebase material after step (a), wherein in step (b), the first metal layeris disposed on the first insulation layer.
 3. The method according toclaim 1, further comprising a step of forming at least one electricaldevice after step (b), wherein the at least one electrical device isdisposed on the second surface of the base material.
 4. The methodaccording to claim 1, wherein step (b) comprises the following steps:(b1) forming a first seed layer on the base material; (b2) forming afirst photoresist on the first seed layer, so as to cover part of thefirst seed layer and expose part of the first seed layer; (b3) forming afirst plated layer on the exposed part of the first seed layer; and (b4)removing the first photoresist and the covered part of the first seedlayer, wherein the first plated layer and part of the first seed layerform the first metal layer.
 5. The method according to claim 1, whereinstep (c) comprises the following steps: (c1) forming a second metallayer on the first lower electrode and anodizing the second metal layer,so as to form a first oxidation layer; (c2) forming a third metal layeron the first oxidation layer; (c3) forming a second photoresist on thethird metal layer; and (c4) removing part of the first oxidation layerand part of the third metal layer, so as to form the first dielectriclayer and the first upper electrode, respectively, and form the firstcapacitor; and (c5) removing the second photoresist.
 6. The methodaccording to claim 1, wherein in step (d), the first protective layercomprises at least one first opening, and the first opening exposes partof the first metal layer or part of the first upper electrode.
 7. Amethod for making a semiconductor package, comprising the steps of: (a)providing a base material, wherein the base material comprises at leastone groove, at least one conductive via structure, a first surface and abottom surface, the groove opens at the first surface of the basematerial, and the conductive via structure is disposed in the groove andexposed on the first surface; (b) forming a first metal layer on thefirst surface of the base material, wherein the first metal layercomprises a first inductor and a first lower electrode, and directlycontacts the conductive via structure; (c) forming a first dielectriclayer and a first upper electrode on the first lower electrode, whereinthe first dielectric layer is disposed between the first upper electrodeand the first lower electrode, and the first upper electrode, the firstdielectric layer and the first lower electrode form a first capacitor;and (d) forming a first protective layer, so as to encapsulate the firstinductor and the first capacitor.
 8. The method according to claim 7,further comprising a step of forming a first insulation layer on thefirst surface of the base material after step (a), wherein in step (b),the first metal layer is disposed on the first insulation layer.
 9. Themethod according to claim 7, further comprising the following stepsafter step (d): (e) disposing the base material on a carrier, whereinthe first surface of the base material faces the carrier; (f) removingpart of the base material from the bottom surface, to form a secondsurface and to expose the conductive via structure on the secondsurface, so as to form a through via structure; (g) forming at least oneelectrical device on the second surface of the base material; and (h)removing the carrier.
 10. The method according to claim 9, furthercomprising a step of forming at least one electrical device after step(h), wherein the at least one electrical device is disposed on thesecond surface of the base material.
 11. The method according to claim7, wherein step (b) comprises the following steps: (b1) forming a firstseed layer on the base material; (b2) forming a first photoresist on thefirst seed layer, so as to cover part of the first seed layer and exposepart of the first seed layer; (b3) forming a first plated layer on theexposed part of the first seed layer; and (b4) removing the firstphotoresist and the covered part of the first seed layer, wherein thefirst plated layer and part of the first seed layer form the first metallayer.
 12. The method according to claim 7, wherein step (c) comprisesthe following steps: (c1) forming a second metal layer on the firstlower electrode and anodizing the second metal layer, so as to form afirst oxidation layer; (c2) forming a third metal layer on the firstoxidation layer; (c3) forming a second photoresist on the third metallayer; and (c4) removing part of the first oxidation layer and part ofthe third metal layer, so as to form the first dielectric layer and thefirst upper electrode, respectively, and form the first capacitor; and(c5) removing the second photoresist.
 13. The method according to claim7, wherein in step (d), the first protective layer comprises at leastone first opening, and the first opening exposes part of the first metallayer or part of the first upper electrode.
 14. A method for making asemiconductor package, comprising the steps of: (a) providing a basematerial, wherein the base material comprises at least one groove, atleast one conductive via structure, a top surface and a second surface,the groove opens at the second surface of the base material, and theconductive via structure is disposed in the groove and exposed on thesecond surface of the base material; (b) forming a first metal layer onthe base material, wherein the first metal layer comprises a firstinductor and a first lower electrode, and directly contacts theconductive via structure; (c) forming a first dielectric layer and afirst upper electrode on the first lower electrode, wherein the firstdielectric layer is disposed between the first upper electrode and thefirst lower electrode, and the first upper electrode, the firstdielectric layer and the first lower electrode form a first capacitor;and (d) forming a first protective layer, so as to encapsulate the firstinductor and the first capacitor.
 15. The method according to claim 14,further comprising a step of forming a first insulation layer on thebase material after step (a), wherein in step (b), the first metal layeris disposed on the first insulation layer.
 16. The method according toclaim 14, further comprising the following steps after step (a): (a1)forming at least one electrical device on the second surface of the basematerial; (a2) disposing the base material on a carrier, wherein thesecond surface of the base material faces the carrier; and (a3) removingpart of the base material from the top surface, to form a first surfaceand to expose the conductive via structure on the first surface, so asto form a through via structure.
 17. The method according to claim 16,wherein in step (b), the first metal layer is disposed on the firstsurface of the base material.
 18. The method according to claim 14,wherein step (b) comprises the following steps: (b1) forming a firstseed layer on the base material; (b2) forming a first photoresist on thefirst seed layer, so as to cover part of the first seed layer and exposepart of the first seed layer; (b3) forming a first plated layer on theexposed part of the first seed layer; and (b4) removing the firstphotoresist and the covered part of the first seed layer, wherein thefirst plated layer and part of the first seed layer form the first metallayer.
 19. The method according to claim 14, wherein step (c) comprisesthe following steps: (c1) forming a second metal layer on the firstlower electrode and anodizing the second metal layer, so as to form afirst oxidation layer; (c2) forming a third metal layer on the firstoxidation layer; (c3) forming a second photoresist on the third metallayer; and (c4) removing part of the first oxidation layer and part ofthe third metal layer, so as to form the first dielectric layer and thefirst upper electrode, respectively, and form the first capacitor; and(c5) removing the second photoresist.
 20. The method according to claim14, wherein in step (d), the first protective layer comprises at leastone first opening, and the first opening exposes part of the first metallayer or part of the first upper electrode.